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cmos 5 v/ + 5 v, 4 dual spst switches adg621/adg622/adg623 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result fro m its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one tech nology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2001 C 2009 analog devices, inc. all rights reserved. f e at u res 5.5 (maximum ) on resistance 0.9 (maximum ) on resistance flatness 2.7 v to 5.5 v single supply 2.7 v to 5.5 v dual supply rail - to - rail operation 10- lead msop package typical power consumption (<0.01 w) ttl - /cmos - compatible inputs applications automatic test equipment power routing communication systems data acquisition systems sample - and - hold systems avionics relay replacement s battery - powered systems g eneral d escription the adg621/adg622/ adg623 are monolithic, cmos , single - pole, single - thro w ( spst ) switches. each switch of the adg621/adg622/adg623 conducts equally well in both directions when on. the adg621/adg622/adg623 contain two independent switches. the adg621 and adg622 differ only in that both switches are normally open and normally c los ed . in the adg62 3, switch 1 is normally open , and switch 2 is normally closed. the adg623 exhibits break - before - make switching action. the adg621/adg622/adg623 offer low on resistance of 4 ?, which is matched to within 0.25 ? between channels. these sw itches also provide low power dissipation yet give high switching speeds. the adg621/adg622/adg623 are available in a 10 - lead msop package. f unctional b lock d iagrams adg621 in1 d2 s2 s1 d1 in2 notes 1. switches shown for a logic 0 input 02616-001 figure 1. adg622 in1 d2 s2 s1 d1 in2 notes 1. switches shown for a logic 0 input 02616-002 figure 2. adg623 in1 d2 s2 s1 d1 in2 notes 1. switches shown for a logic 0 input 02616-003 figur e 3. p roduct h ighlights 1. low on resistance , r on (4 ? typ ical ). 2. dual 2.7 v to 5.5 v or single + 2.7 v to + 5.5 v. 3. low power dissipation ; cmos construction ensures low power dissipation. 4. tiny 10 - lead msop package.
adg621/adg622/adg623 rev. b | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dual supply ................................................................................... 3 single supply ................................................................................. 4 absolute maximum ratings .............................................................5 esd caution ...................................................................................5 pin configuration and function descriptions ..............................6 terminology .......................................................................................7 typical performance characteristics ..............................................8 test circuits ...................................................................................... 10 outline dimen sions ........................................................................12 ordering guide ............................................................................ 12 revision history 11/09 r ev. a to re v. b changes to table 5 ............................................................................ 5 changes to ordering guide .......................................................... 12 6/0 7 r ev. 0 to rev. a change to on resistance flatnes s, r flat( on) specification (table 1) ...................................................................... 3 change to on resistance flatnes s, r flat(on) specification (table 2) ...................................................................... 4 added table 6 .................................................................................... 6 changes to terminology section .................................................... 7 changes to figure 13 ........................................................................ 9 updated outline dimensions ....................................................... 12 changes to ordering guide .......................................................... 12 11/0 1 revision 0: initia l ver si o n
adg621/adg622/adg623 rev. b | page 3 of 12 specifications dual supply 1 v dd = +5 v 10% , v ss = ?5 v 10%, gnd = 0 v , unless otherwise noted. table 1. parameter +25c ? 40c to +85c unit test conditions/comments analog switch analog signal range v ss to v dd v v dd = + 4.5 v, v ss = ?4.5 v on resistance, r on 4 ? typ v s = 4.5 v, i s = ?10 ma, see figure 16 5.5 7 ? max on resistance match between channels , ?r on 0.25 ? typ v s = 4.5 v, i s = ?10 ma 0.35 0.4 ? max on resistance flatness , r flat(on) 0.9 0.9 ? typ v s = 3.3 v, i s = ?10 m a 1.5 ? max leakage currents v dd = + 5.5 v, v ss = ?5.5 v source off leakage , i s (off ) 0.01 na typ v s = 4.5 v, v d = ? 4.5 v, see figure 17 0.25 1 na max drain off leakage , i d (off ) 0.01 na typ v s = 4.5 v, v d = ? 4.5 v , see figure 17 0.25 1 na max channel on leakage , i d , i s ( on ) 0.01 na typ v s = v d = 4.5 v, see figure 18 0.25 1 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current , i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2 pf typ dynamic characteristics 2 t on 75 ns typ r l = 300 ?, c l = 35 pf; v s = 3.3 v, see figure 19 120 155 ns max t off 45 ns typ r l = 300 ? , c l = 35 pf; v s = 3.3 v, see figure 19 70 85 ns max break -before- make t ime delay, t bbm (adg623 only) 30 ns typ r l = 300 ?, c l = 35 pf; v s1 = v s2 = 3.3 v 10 ns min see figure 20 charge injection 110 pc typ v s = 0 v, r s = 0 ? , c l = 1 nf, see figure 21 off isolation ?65 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz, see figure 22 channel - to - channel crosstalk ?90 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz, see figure 23 bandwidth ?3 db 230 mhz typ r l = 50 ? , c l = 5 pf, see figure 24 c s ( off ) 20 pf typ f = 1 mhz c d (off ) 20 pf typ f = 1 mhz c d , c s ( on ) 70 pf typ f = 1 mhz power requirements v dd = 5.5 v, v ss = C 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max i ss 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max 1 temperature range is as follows: b v ersion , C 40c to +85c. 2 guaranteed by design ; not subject to production test.
adg621/adg622/adg623 rev. b | page 4 of 12 single supply 1 v dd = 5 v 10%, v ss = 0 v, g n d = 0 v, unless otherwise noted . table 2. parameter +25c C 40c to +85c unit test conditions/comments analog switch analog signal range 0 to v dd v v dd = 4.5 v, v ss = 0 v on resistance , r on 7 ? typ v s = 0 v to 4.5 v, i s = C 10 ma, see figure 16 10 12.5 ? max on resistance match between channels , ?r on 0.5 ? t yp v s = 0 v to 4.5 v, i s = ?10 ma 0.75 1 ? max on resistance flatness , r flat(on) 0.5 0.5 ? typ v s = 1.5 v to 3.3 v, i s = ?10 ma 1.2 ? max leakage currents v dd = 5.5 v source off leakage i s (off ) 0.01 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v, see figure 17 0.25 1 na max drain off leakage i d (off ) 0.01 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v, see figure 17 0.25 1 na max channel on leakage , i d , i s ( on ) 0.01 na typ v s = v d = 1 v/4.5 v , see figure 18 0.25 1 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current , i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2 pf typ dynamic characteristics 2 t on 120 ns typ r l = 300 ?, c l = 35 pf; v s = 3.3 v, see figure 19 210 260 ns max t off 50 ns typ r l = 300 ?, c l = 35 pf; v s = 3.3 v, see figure 19 75 100 ns max break -before- make time delay, t bbm (adg623 only) 70 ns typ r l = 300 ?, c l = 35 pf, v s1 = v s2 = 3.3 v 10 ns min s ee figure 20 charge injection 6 pc typ v s = 0 v; r s = 0 ?, c l = 1 nf, see figure 21 off isolation C65 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz, see figure 22 channel - to - channel crosstalk C90 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz, see figure 23 bandwidth ?3 db 230 mhz typ r l = 50 ? , c l = 5 pf, see figure 24 c s ( off ) 20 pf typ f = 1 mhz c d (off ) 20 pf typ f = 1 mhz c d , c s ( on ) 70 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max 1 temperature range is as follows: b version, C 40c to +85c. 2 guaranteed by design ; not subject to production test.
adg621/adg622/adg623 rev. b | page 5 of 12 absolute maximum rat ings t a = 25 c, unless otherwise noted. table 3. parameter rating v dd to v ss 13 v v dd to gnd ? 0.3 v to +6.5 v v ss to gnd +0.3 v to C 6.5 v analog inputs 1 v ss C 0.3 v to v dd + 0.3 v digital inputs 1 C 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (p ulsed at 1 ms, 10% duty c ycle max imum ) continuous current, s or d 50 ma operating temperature range industrial (b version) C 40 c to +85 c storage temperature range C 65 c to +150 c junction temperature 150 c msop package ja thermal impedance 206 c/w jc thermal impedance 44 c/w lead soldering lead temperature, soldering (10 sec) 300 c ir reflow, peak temperature 220 c pb - free soldering reflow, peak temperature 260(+0/ ? 5)c time at peak temperature 20 sec to 40 se c 1 overvoltages at in x , s, or d must be clamped by internal diodes. current s should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. only one absolute maximum rating may be applied at any one time. table 4. adg621/adg622 truth table adg621 in x adg622 in x switch s x condition 0 1 off 1 0 on table 5. adg623 truth table in1 in2 switch s1 switch s2 0 0 off on 0 1 o ff o ff 1 0 on on 1 1 on off esd caution
adg621/adg622/adg623 rev. b | page 6 of 12 pin configuration and function des criptions nc = no connect s1 1 d1 2 in2 3 gnd 4 v ss 5 v dd 10 in1 9 d2 8 s2 7 nc 6 top view (not to scale) adg621/ adg622/ adg623 02616-004 figure 4 . 10 - lead msop (rm - 10) table 6 . pin function descriptions pin no. mneonic description 1, 7 s 1, s2 source terminal. may be an input or an output. 2, 8 d1, d2 drain terminal. may be an input or an output. 3, 9 in2, in1 control input . 4 gnd ground (0 v) reference . 5 v ss most negative power s upply in a dual - supply a pplication. i n single - supply applications , this should be tied to ground at the device. 6 nc no connect. 10 v dd mo st positive power supply potential .
adg621/adg622/adg623 rev. b | page 7 of 12 terminology i dd positive supply current. i ss negative supply current v d (v s ) analog voltage on terminal d and te r m i n a l s. r on ohmic resistance between te r m i n a l d and te r m i n a l s. r flat (on) on resistance fl atn ess is d efined as the difference between the maximum and minimum val ue of on resistance as measured over the specified analog signal range. ?r on on resistance match between any two channels. i s ( off ) source leakage current with the switch off. i d ( off ) drain leak age current with the switch off. i d , i s ( on) channel leakage current with the switch on. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. c s ( off ) off switch source capacitance . measured with reference to ground. c d ( off ) off switch drain capacitance. measured with reference to ground. c d , c s ( on ) on switch capacitance. measured with reference to ground. c in digital input capacitance. t on delay time between the 50% and the 90% points of the digital input and switch on condition. t off delay time between the 50% and the 90% points of the digital input and switch off condition. t bbm on or off time measured between the 9 0% points of both switches when switching from one address stat e to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during on - off switching . off isolation a measure of an unwanted signal coupling through an off switch. crosstalk a measure of an unwante d signal that is coupled through from one channel to another as a result of parasitic capacitance. ?3 db bandwidth the frequency at which the output is attenuated by 3 db . on response the frequency response of the on switch. insertion loss the attenuation between the input and output ports of the switch when th e switch is in the on condition and is due to the on resistance of the switch.
adg621/adg622/adg623 rev. b | page 8 of 12 typical performance characteristics 02616-005 on resistance ( ?) 8 7 6 5 4 3 2 1 0 v d , v s (v) ?5 ?4 ?3 ?2 ?1 0 1 2 3 54 v dd , v ss = 2.5v t a = 25c v dd , v ss = 3v v dd , v ss = 3.3v v dd , v ss = 4.5v v dd , v ss = 5v figure 5 . on resistance vs. v d , v s (dual supply) 02616-006 v dd = 2.7v v dd = 3v v dd = 3.3v v dd = 4.5v v dd = 5v t a = 25c v ss = 0v v d , v s (v) on resistance ( ?) 20 0 16 12 8 4 1 2 3 4 5 0 figure 6 . on resistance vs. v d , v s (single supply) 02616-007 v d , v s (v) on resis t ance ( ?) 6 ?5 5 4 3 2 1 0 ?3 ?1 1 5 3 ?4 ?2 0 2 4 v dd = +5v v ss = ? 5v t a = +85c t a = +25c t a = ? 40c figure 7 . on resistance vs. v d , v s for different temperatures (dual supply) 02616-008 v d , v s (v) on resis t ance ( ?) 0 1 2 3 5 4 10 8 6 4 2 0 9 7 5 3 1 t a = +85 c t a = +25 c t a = ? 40c v dd = 5v v ss = 0v figure 8 . on resistance vs. v d , v s for different temperature (single supply) tempera ture (c) leakage current (na) 0 10 20 30 40 50 60 70 80 0.5 ?0.5 0.2 0.4 0.3 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 i d (off) i d , i s (on) i s (off) v dd = +5v v ss = 0v v d = 4.5v v s = 4.5v 02616-009 figure 9 . leakage current vs. temperature (dual supply) tempera ture ( c) leakage current (na) 0 10 20 30 40 50 60 70 80 0.5 ?0.5 0.2 0.4 0.3 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 i d (off) i d , i s (on) i s (off) v dd = 5v v ss = 0v v d = 4.5v/1v v s = 1v/4.5v 02616-010 figure 10 . leakage current vs. temperature (single supply)
adg621/adg622/adg623 rev. b | page 9 of 12 02616-0 11 v s charge injection (pc) 250 ?5 ?4 ?3 ?2 ?1 0 1 2 3 5 t a = 25c 200 150 100 50 0 4 v dd = +5v v ss = 0v v dd = +5v v ss = ?5v figure 11 . charge injection vs. source voltage temperature (c) ?40 ?20 0 20 40 60 80 time (ns) 180 160 0 80 60 40 20 140 100 120 t on t off v dd = +5v v ss = 0v v dd = +5v v ss = ?5v v dd = +5v v ss = ?5v v dd = +5v v ss = 0v 02616-012 figure 12. t on /t off times vs. temperature 02616-013 0.2 1 10 100 frequenc y (mhz) a ttenu a tion (db) v dd = +5v v ss = ?5v t a = 25c 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 figure 13 . off isolation vs. frequency 02616-014 0.2 1 10 100 frequenc y (mhz) a ttenu a tion (db) v dd = +5v v ss = ?5v t a = 25c 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 figure 14 . crosstalk vs. frequency 0.2 1k 10 v dd = +5v v ss = ?5v t a = 25c 1 100 frequenc y (mhz) a ttenu a tion (db) 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 02616-015 figure 15 . on response vs. frequency
adg621/adg622/adg623 rev. b | page 10 of 12 test circuits i ds v1 s d v s r on = v1/i ds 02616-016 s d v s v d i s (off) i d (off) a a 02616-017 s d v d i d (on) a 02616-018 nc nc = no connect figure 16 . on resistance figure 17 . off leakage figure 18 . on leakage 0.1f v s in s d v dd gnd r l 300? c l 35pf v out v dd v in v in v out t on t off 50% 50% 90% 90% 50% 50% v ss v ss 0.1f adg621 adg622 02616-019 figure 19 . switching times (t on , t off ) s1 d1 0.1f v dd in1, in2 v s1 gnd r l1 300? c l1 35pf v out1 v s2 v out2 r l2 300? c l2 35pf s2 v in d2 v dd t bbm t bbm 50% 50% 90% v in v out1 v out2 90% 90% 90% 0v 0v 0v 0.1f v ss v ss 02616-020 figure 20 . break - before - make time dela y, t bbm (a dg623 only) s d v dd in v s gnd c l 1nf v out r s v dd sw on v in v out q inj = c l v out sw off v ss v ss v out 02616-021 figure 21 . charge injection
adg621/adg622/adg623 rev. b | page 11 of 12 network ana lyzer v dd v ss 0.1f 0.1f v dd v ss in v in s d off isol a tion = 20 log v out v s gnd 50? 50? r l 50? v s v out 02616-022 figure 22 . off isolation channel- t o-channe l cross t alk = 20 log network ana lyzer v dd v ss 0.1f 0.1f v dd v ss in v out v s gnd 50? r l 50? v s v out 02616-023 d1 s1 s2 d2 r 50? r 50? figure 23 . channel - to - channel crosstalk network ana lyzer v dd v ss 0.1f 0.1f v dd v ss in v in s d insertion loss = 20 log v out with switch v out without switch gnd 50? r l 50? v s v out 02616-024 figure 24 . bandwidth
adg621/adg622/adg623 rev. b | page 12 of 12 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 25. 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters ordering guide model temp erature range package description package option branding adg621brm C 40c to +85c 10- lead mini small outline package [msop] rm - 10 sxb adg621brm C reel7 C 40c to +85c 10- lead mini small outline package [msop] rm - 10 sxb adg621brm z 1 C 40c to +85 c 10- lead mini small outline package [msop] rm - 10 sxb# adg621brm z- reel 1 C 40c to +85c 10- lead mini small outline package [msop] rm - 10 sxb# adg622brm C 40c to +85c 10- lead mini small outline package [msop] rm - 10 syb adg622brm - reel C 40c to +85c 10- lead mini small outline package [msop] rm - 10 syb adg622brm - reel7 C 40c to +85c 10- lead mini small outline package [msop] rm - 10 syb adg622brm z 1 C 40c to +85c 10- lead mini small ou tline package [msop] rm - 10 s12 adg622brm z- reel 1 C 40c to +85c 10- lead mini small outline package [msop] rm - 10 s12 adg622brm z- reel7 1 C 40c to +85c 10- lead mini small outline package [msop ] rm - 10 s12 adg623brm C 40c to +85c 10- lead mini small outline package [msop] rm - 10 szb adg623brm - reel C 40c to +85c 10- lead mini small outline package [msop] rm - 10 szb adg623brm - reel7 C 40c to +85c 10- lead mini small outline package [msop] rm- 10 szb adg623brm z 1 C 40c to +85c 10- lead mini small outline package [msop] rm - 10 szb # adg623brm z- reel 1 C 40c to +85c 10- lead mini small outline package [msop] rm - 10 szb # adg623brm z-r eel7 1 C 40c to +85c 10- lead mini small outline package [msop] rm - 10 szb # 1 z= rohs compliant part, # denotes rohs compliant product and may be top or bottom marked. ? 2001 C 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks ar e the property of their respective owners. d 0 2616 -0- 11/09(b)

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